Epiphany-IV 64-core Microprocessor (E64G401) (End of Life)

The Epiphany-IV_400x400E64G401 is 64-core microprocessor/coprocessor reference design based on the 4th generation of the Epiphany multicore architecture that was designed as a direct replacement of the E16G301. The Epiphany™ architecture defines a multicore, scalable, shared memory, parallel computing fabric and consists of a 2D array of compute nodes connected by a low-latency mesh network-on-chip. The main components of the E64G401 product are shown below. For more detailed information about the Epiphany architecture, please refer to the Epiphany Architecture Reference Manual.


Download E64G401 Datasheet (PDF)


We have depleted our stock of Epiphany-IV silicon devices and there are no plans to produce any more.


  • 64 High Performance RISC CPU Cores
  • 800 MHz Operating Frequency
  • 102 GFLOPS Peak Performance
  • 1.6 TB/s Local Memory Bandwidth
  • 102 GB/s Network-On-Chip Bisection Bandwidth
  • 6.4 GB/s Off-Chip Bandwidth
  • 2 MB On-Chip Distributed Shared Memory
  • 2 Watt Maximum Chip Power Consumption
  • IEEE Floating Point Instruction Set
  • Fully-featured ANSI-C/C++ programmable
  • GNU/Eclipse based tool chain
  • Source synchronous sub-LVDS off chip links for host or direct chip-to-chip interfacing.
  • Chip to chip links for integrating up to 64 chips on a single board
  • 324-ball 15x15mm flip-chip BGA

RISC Processor:
Each compute node contains an independent superscalar floating-point RISC CPU operating at 800 MHz and 1.6 GFLOPS/sec. The CPU has an efficient general-purpose instruction set that excels at compute intensive applications while being efficiently programmable in C/C++ without any need to write code using assembly or processor specific intrinsics.

Memory System:
The Epiphany memory architecture is based on a flat memory map in which each compute node has a small amount of local memory as a unique addressable slice of the total 32-bit address space. A processor can access its own local memory and other processors memory through regular load/store instructions, with the only difference being the latency and effective throughput of the transactions. The local memory system is comprised of 4 separate banks, allowing for simultaneous memory access by the instruction fetch engine, local load-store instructions, and by load/store transactions initiated by other processors within system.

The eMesh Network-on-Chip is a 2D mesh network that handles all on-chip ad off-chip communication. The network is based on atomic 32- bit memory transactions and is transparent to the program running. The network consists of three separate and orthogonal mesh structures, each serving different types of transaction traffic: one network for on-chip write traffic, one network for off chip write traffic, and one network for all read traffic.

Off-Chip IO:
The eMesh network and memory architecture is extended off-chip using source synchronous LVDS based serial links that provide up to 1.6GB/sec of effective bandwidth per link. Each E16G401 has 4 links, one in each direction (north, east, west, south), allowing chips to be easily interfaced with FPGAs and/or other E16G401 chips on a board.

System Examples:
The E16G401 product can be used in a number of different system configurations, some of which are shown in this section.


Potential Applications

  • Smart-phones and tablet app acceleration
  • High end audio
  • Computational photography
  • Speech Recognition
  • Face detection/recognition

Computing Infrastructure:

  • Super Computers
  • Big Data Analytics
  • Software Defined Networking
  • Data-center Appliances
  • High Frequency Trading


  • Radar/Sonar
  • Extremely Large Sensor Imaging
  • Hyperspectral Imaging
  • Communication Jamming
  • Military Radios
  • Munitions/Guidance


  • Ultrasound
  • CT


  • Communication test-bed
  • Software defined radio
  • Adaptive Pre-distortion


  • Machine Vision
  • Autonomous Robots/Navigation
  • Automotive Safety
  • High Speed Data Acquisition/Generation


  • Compression
  • Security Cameras
  • Video Transcoding


  1. Much like everybody else, I would be interested if there was at least a rough time frame in which the Epiphany-IV was available. I can hardly wait to get my hands on one of those for use in autonomous robot navigation. A theoretical 100 Gflops at a mere 2W footprint suddenly brings some interesting options to the table, such as computer vision.
    Thanks :)

    • same as you ma’ man … just drooling over a prospect of 4 to 8 of those running with a full duplex of hack RF … :) throw in a r-pi just for fun and bundle the lot in a tool-case with a 10′ touchscreen… so yeah … can hardly wait

  2. As someone working on super-computers (Vital-IT in the Swiss Institute of Bioinformatics) I am really interested by this beast. Nice platform to play around and experiment on parallel algorithms.

    For all those who missed the initial Kickstarter:
    Do you plan a similar fund-raiser for the “next-gen” Parallela board (around this newer Epiphany IV) ?
    – I would like to support further improvement of the boards
    – I would appreciate getting one Epiphany-IV board once it’s out.
    (But as said, I missed the initial Kickstarter)

  3. Hi, I am interested in testing out your technology for my upcoming prototype which is going to be deployed in mid 2014, please let me know your best communication channel,

    Thank you,

    • Good nigth, I’m Gilberto and I want known if you can used the product for mining Cryptocoins? I want know How do you do? thanks

  4. Great stuff, but This page could do with an update – it refers to arch of the 16x chip . I was wondering whether the 64x chip will still only have 4 links?

  5. Is it possible to by the 64 core version of the Parallella? I just checked your shop and I didn’t see it available. Has the release date been moved to 2015?


  6. can anyone state how many 64 core microprocessors have shipped; i.e. how many have been (or could potentially be) deployed beyond the adapteva campus …?

    also, is anyone aware of a secondary market for these units?



  7. Any updates on availability? I would be happy to order 4 at once they are available (assuming they cost less than 500$ each). :)

  8. I see that you already have the 64 core Epiphany-IV board. Can I purchase and array of them such as in the A-1 you announced in Leipzig this summer?

  9. Hi AGAIN from TÜBINGEN UNIVERSITY, Schwaben,S. Germany… I ordered the 64-CORE STAND-ALONE COMPUTER nearly 3 years ago…. Are you really going to be selling this in a reasonable time?… Or have the BIG-BOYS in the industry put a block on it ? If NOT then please have the decency to say so. Another puzzle to me is why CANONICAL ( sponsor of UBUNTU ) DOESN’T mention your company at all, or even support you ?

  10. You have this in this website:


    We have depleted our stock of Epiphany-IV silicon devices and there are no plans to produce any more.

    what is NEXT??? after 16 core epiphany right now being used in parallella board..
    what is the future of multi core epiphany architecture..Come up with future after parallella 16…

  11. Will there be a 4 port USB 2 or USB 3 version? This Ethernet port is great but wastes 80 to 90 percent of data in TCP/IP overhead if you go directly from one board to another. A bus or bus stackable version would be great. Movidius has not released fathom USB stick neural computer yet and would like to test that with a pi board of whatever flavor – perhaps interface it with this board. An FPGA USB stick may prove useful.

    So, what I’m getting at is a common architecture to incorporate various platforms may prove useful. Rasberry pi, Arduino standardized an interface and others followed into explosive growth and sales.

    That said, having read some of the epiphany architecture docs I find interest in this platform.

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