A 1024-core 70 GFLOPS/W Floating Point Manycore Microprocessor

(HPEC 2011): This paper describes the implementation of a software programmable floating point multicore architecture scalable to thousands of cores on a single die. A 1024 core implementation at 28nm occupies less 128mm2 and has a simulated energy efficiency of 70 GFLOP/Watt with a peak performance of 1.4 TFLOP. The aggressive claims are supported by a 65nm silicon proven 16-core version of the same design with measured efficiency of 35 GFLOPS/Watt.Read More…

Posted in White Papers and tagged , , .

Leave a Reply Using Facebook or Twitter Account