Epiphany Introduction

The industry is facing daunting challenges in the move towards parallel computation as the current approach is hitting the wall hard.


“The Epiphany”

At Adapteva, we believe that the future of computing is parallel and heterogeneous and have set out to create a clean slate architecture optimized with these assumptions in mind. This has allowed us us to throw away tons of legacy overhead that has accumulated in existing approaches over the years, resulting in an architecture that is easy to use while achieving unprecedented energy efficiency. The following picture shows a high level overview of the Epiphany multicore architecture.

The Epiphany has a flat 32 bit address space split into 4096 1-MiB chunks. Each core is assigned his own 1-MiB chunk, but it also has transparent access to the memory of every other core in the system. Each individual core is a high performance RISC processor that can be programmed using the standard programming methods from the last 40 years. The challenge with having so many processors to work with is getting them to work well together. There are many parallel programming approaches in existence today, including: openCL, openMP, and MPI.  By virtue of being a general purpose programmable processor, the Epiphany architecture could potentially support all of them with some effort.



The Epiphany addresses clear weaknesses in the existing offering of computing platforms, namely:

  • Ease of Use: Sixty years of computing has clearly demonstrated that the imagination and productivity of programmers is boundless once  a productive hardware platform is in place.  The Epiphany architecture  is ANSI-C programmable and only imposes a minor change to the von  Neumann programming model that has been the industry standard for many  decades.  To make math processing easy, the Epiphany architecture  supports IEEE floating point data formats, allowing a significant reduction in time to market and development cost compared to a hardware based development platform.
  • Low Power: In advanced systems, maximum performance is limited by power consumption, so computing energy efficiency is paramount.  To maximize computing energy efficiency, Epiphany architectural features were only included after they had demonstrated that they improved overall energy computing energy efficiency after going through a complete chip implementation cycle.
  • Scalability: Future performance gains will need to come from increased parallelism and not from more powerful cores.  The Epiphany  architecture was designed from day one scale to thousands of cores on a single chip and millions of cores within a larger system.






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