The Epiphany-III chip was taped out in 2010 and the Epiphany-IV chip was taped out in 2011. Both chips contained a number of experimental multi-core features that were never disclosed. We put these features into the chip because we thought they might be useful, but we never had the resources to properly validate them once the silicon arrived.
We are now pleased to announce that thanks to the tireless testing of our hard working summer interns we are ready to disclose some of these features. Why didn’t we disclose it earlier? Well, to quote one of the giants: “Make it right before you make it faster.” We now have a basic SDK that works great and it’s time to turn on some of these hardware optimization features. Some of these features like the multicast communication and hardware barriers have such a big impact on communication bandwidth and synchronization penalties that they can actually impact the programming model. We want to make sure most of these features are in full use by the time we start shipping thousands of Parallella boards
Please consider these features experimental and do your best to break them.
New “Secret” Multicore Features:
- Multicore multicast transactions
- Multicore breakpoints
- Multicore hardware barriers
- eMesh network traffic monitoring
- eMesh detour routing
- Hardware loops
- DMA messaging
- Hardware debugging
Here is the new update of the Epiphany Architecture Reference Manual.
Examples demonstrating how to use these features can be found on github:
To give feedback on the specifications, please join the discussion at: