A 25 GFLOPS/Watt Software Programmable Floating Point Accelerator

(HPEC 2010): This paper presents a hybrid approach to high performance embedded computing that uses FPGAs, general purpose processors and a novel floating point accelerator to push the limits of energy efficiency while keeping with today’s well known programming languages and tools. A floating point accelerator has been designed, containing 16 independent ANSI C programmable processors cores, a high throughput Network On Chip and low power FPGA data links. The accelerator chip demonstrates a processing efficiency of 25 GFLOPS/W, and a maximum sustained performance of 32 GFLOPS while operating at 1 GHz. FULL ARTICLE

Posted in White Papers.

Leave a Reply Using Facebook or Twitter Account