Epiphany Architecture Reference Manual 0


The Epiphany architecture defines a multicore, scalable, shared-memory, parallel computing
fabric. The Epiphany architectures is comprised of a scalable 2D array high performance super-scalar floating point RISC processors, a distributed 32-bit shared memory model, and a low latency mesh Network-On-Chip interconnect fabric. The Epiphany architecture reference  manual describes the architecture completely and openly and is written for system developers and programmers. Together with the Epiphany SDK reference manual it should provide all the necessary information needed to design a high performance system.

Epiphany Architecture Reference Manual (PDF)

Table of Contents:

  • Introduction
  • Programming Model
  • Software Development Environment
  • Memory Architecture
  • eMesh Network-On-Chip
  • Processor Node
  • eCore RISC CPU
  • Direct Memory Access Engine
  • Event Timers
  • Appendix A: Instruction Set Architecture Reference
  • Appendix B: Register Set Reference

 

 

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