Low Power Design
Adapteva has created breakthrough multicore
architecture that scales up from a few processors on a
chip to thousands of processors on a single chip. By designing each processor processor sub
component specifically for massive multicore processing and for low power embedded computing, we
were able to remove much of the power inefficiency often seen in traditional microprocessors. Features
found in traditional general purpose processors were examined for power efficiency and were only
included in our architecture if they could clearly demonstrate that they reduced overall power
consumption. The key to achieving the unparalleled power efficiency was the creation of a fast feature
optimization loop that saw every architecture feature go through a complete chip implementation cycle
before being accepted. This way, each feature could be assigned an exact power penalty number rather
than the usual back of the envelope based numbers usually associated with high level architecture
design. Over a span of two years more than 50 complete architectural iterations were completed before
arriving at the final energy optimized architecture. The end result is an architecture that offers the
system developer a 10x immediate improvement in energy efficiency over comparable existing devices.
High Performance Design
It's actually not that difficult to design a low power product if performance is not an issue. The
challenge is keeping the performance high while reducing the power as much as possible. For example,
consider a simple single pipeline stage cpu. It will by definition have very good power efficiency, but
won't have the operating frequency and instruction set needed to process the real time data for most of
today's high bandwidth applications. The Adapteva processor cores is highly pipelined to reach a
1 GHZ operating frequency and has a powerful math centric floating point instruction set. This
awesome processing power makes it a competitive standalone processor on its own right. However the
true power of the architecture comes from the ability to place thousands of these processors on a single
die connected through a powerful NetworkOnChip,
enabling Teraflops
of performance within the
same power envelope usually associated with a single general purpose processor.
Ease of Use:
Great engineers want to focus their effort on solving the problem at hand, not on learning proprietary
architectures and coping with restrictions that are roadblocks in the path of the ideal solution.
Adapteva's new architecture presents a clean "processing fabric" to the expert user the same way a high
quality blank canvas is presented to an artist. It may not be for everyone, but for those skilled in
the art, there is no substitute. Our architecure is ANSIC
programmable, so there is no new language or
extension set deal with. There is also no built in massive instruction level parallelism like
SIMD and VLIW based architecures, which means the user is more likely to get close to the peak
performance in real applications. Many of today's real systems will run at 10% of the peak
performance. By increasing the users efficiency without increasing the programming effort,we have
essentially given the user more performance at the same cost and power.
Scalability:
Adapteva's architecture is designed to be scalable, not only in terms of the number of cores ona chip but
also in terms of future process technology nodes. For the Adapteva chip design team team this means
we can target a new technology node as soon as its available and can tape out any size array within
three months of design start. For the user, the built in scalability means having a single unified
processor core for every application, not many different cores depending onthe level of performance
needed. The only thing that changes between Adapteva's low power products and high performance
products is the number of cores in the product. Using this scalable approach, our products scale from a
single 1GHz core consuming a mere 40mW to a 1000 core product having over 2 Tera Flop of
performance.
Productivity:
Most engineers have a lot of time invested in their existing programming environment and
methodologies. Staying within a single environment over an extended time has enormous productivity
benefits as it lets the programmer focus on solving the problem instead of focusing on problem solving
infrastructure. Adapteva's architecture is true ANSIC
programmable and has a powerful optimizing
compiler, so your existing legacy code or favorite open source library will execute correctly on on our
architecture from day one without modification. Adapteva's multicore programming environment is
based on the exceedingly popular open source GNU compiler, GNU debugger,and Eclipse Integrated
Design environment.